This invention relates to enhancement mode RF devices and methods for fabrication.
More particularly, the present invention relates to enhancement mode RF devices with controlled channel resistance (ON resistance) and breakdown voltage and methods for fabrication which are compatible with other fabrication processes.
One specific type of prior art enhancement mode device is fabricated by providing a wafer with a stack of compound semiconductor layers formed thereon to define a channel. Gate material is deposited on the stack and etched to form a gate overlying the channel. One problem here is that this type of gate formation requires lithographic techniques that seriously limit the size to which a gate can be reduced and, as is known in the art, the size of the gate dictates the operating frequencies. For example, in today""s lithography the gate length has a lower limit of approximately 0.65 xcexcm.
In this prior art fabrication process, the source and drain are next formed by standard implantation techniques (e.g. one or both of the source and drain are formed by a self-aligned process using the gate as a mask) and metal contacts are deposited on the surface of the upper compound semiconductor layer. The implantation in these prior art devices is performed to a depth to form the source and drain in the upper compound semiconductor layers (i.e. the channel layers). Care must be taken to ensure that surface dispersion or improper doping of the area in these layers adjacent to the gate does not occur, especially adjacent the gate on the drain side. This surface dispersion and the position of the source and drain contacts are variables which are difficult to control during fabrication.
Another specific type of prior art enhancement mode device is fabricated by providing a wafer with a stack of compound semiconductor layers, including a cap layer, formed thereon to define a channel. The cap layer is etched to define spaced apart source and drain areas which are implanted to form a source and a drain and the device is covered with a layer of dielectric material. The source and drain implanting is performed using standard photolithography. The dielectric layer is etched to allow deposition of metal in contact with the source and drain and the dielectric and cap layers are etched to define a gate area. Gate metallization is provided in the gate area to form a gate terminal in communication with the channel.
This second type of enhancement mode device has several drawbacks. First, the cap layer is not formed to create a depletion mode behavior in the access (source and drain) regions. Also, the source and drain implants, which are only into contact with the channel, are not deep enough for low access resistance. Further, the channel material, which is simply doped gallium arsenide, is not the best. A layer of aluminum gallium arsenide (AlGaAs) is deposited between the channel layer and the cap layer and the source and drain metal contacts are positioned on the AlGaAs layer, which results in less consistent contacts. Finally, there is less flexibility in the AlGaAs thickness and in the channel doping, which limits the ultimate performance. Thus, because of shallow implants and unoptimized channel material, it is difficult to reduce or minimize the channel resistance.
Accordingly it is highly desirable to provide enhancement mode RF devices which overcome these drawbacks and, in particular to provide enhancement mode RF devices with controlled channel resistance (ON resistance) and breakdown voltage. It is highly desirable to provide an improved method of fabrication which is compatible with other fabrication processes and which can provide mixed-mode integration if desirable.